The Infinity Engine is SandLogic's chip-level mechanism that lets one piece of silicon run every model architecture — convolutional networks, recurrent networks, Transformers, linear-attention models, and state-space models. Chip vendors today force device makers to pick a workload family at design time and live with the choice for years while AI architectures shift every few months. The Infinity Engine inverts that math: one chip, every architecture, future-relevant.
The AI silicon market today asks device makers to commit, at design time, to which model family the chip will run. Vision chips for cameras. LLM chips for assistants. Separate speech chips if voice matters. Each one a different SKU, a different driver stack, a different supply contract — and a different roadmap with its own obsolescence clock.
The BOM decision today forces device makers to pick the workload family up front. A smart-TV chip that does vision can't do conversational AI. An LLM accelerator can't run YOLO with any throughput. Voice needs a different SKU again.
Mamba broke transformer dominance in late 2023. RWKV-7 dropped in 2025. New architectures will emerge through 2026 and beyond. Each one demands different kernels — and most chips can't absorb them without redesign.
Silicon takes 18-36 months to design and tape out. AI architectures shift every 6-12 months. A chip designed in 2024 to run "what's hot now" is a chip that ships in 2027 unable to run what's hot then — unless its architecture absorbs new model families through software, not silicon.
The Infinity Engine is the chip-level mechanism inside Krsna that lets one piece of silicon run every model architecture. It is the result of silicon and compiler engineered together — the chip ships the union of operators current and emerging architectures need, and CORE compiles each architecture down to that operator set.
The MAC arrays, on-die memory, and operator set are engineered as the union of what current AND emerging AI architectures need. Matmul and attention for transformers. Convolution for CNNs. Scan for state-space models. Recurrence and gating for RNN / LSTM. The chip ships the superset; the compiler picks the subset.
Krsna SoC architecture →CORE recognizes the incoming model architecture (transformer attention vs SSM scan vs CNN convolution vs RNN recurrence) and emits the appropriate kernel sequence. Built on IREE — the open MLIR-based compiler runtime. PyTorch, TensorFlow, and JAX models go in. A deployable artifact comes out. New architectures land as new compilation paths.
EdgeMatrix · CORE layer →The Infinity Engine architecture supports the model families that ship in real products today — and is engineered to absorb the architectures that emerge next.
ResNet · YOLO · VGG · MobileNet · ConvNeXt
The architecture every camera-class device runs. Most LLM accelerators treat CNNs as an afterthought; the Infinity Engine treats convolution as first-class.
Classical sequence models · time-series · control loops
The architecture that powered sequence modeling before transformers. Still in production for time-series forecasting, sensor fusion, and on-device control workloads.
Llama · Shakti · Qwen · Mistral · Gemma · DeepSeek
The architecture that dominates current enterprise AI. Attention-based, parallel-friendly. Production support across the variant family on Krsna today.
RWKV-5 (Eagle) · RWKV-6 (Finch) · RWKV-7 (Goose)
RNN-style with constant memory and linear time complexity. Important for ultra-long-context and on-device workloads where transformer memory cost is prohibitive.
Mamba · Mamba-2 · Jamba (hybrid)
Linear-time alternatives to attention. The architecture that broke the transformer monopoly in 2023. Production-validated on Krsna via SambaASR.
Whisper · Moonshine · Sruthi · Svara
The architecture voice agents, dictation, and translation workloads depend on. End-to-end on-chip support — STT, TTT, and TTS in one inference pipeline.
The Infinity Engine isn't an architectural curiosity — it's a commercial argument. The investment device makers put into Krsna pays back across product lines, generations, and the architectures that haven't shipped yet. Three dimensions where one chip beats many.
One accelerator across product lines — the same chip in the smart-TV that does vision and the assistant device that does language. Today's alternative: separate silicon SKUs per workload family, separate supply contracts, separate driver stacks. Infinity Engine collapses that BOM tax.
Chips have 2-3 year lifecycles. AI architectures shift every 6-12 months. A chip designed in 2024 to run "what is hot now" is a chip shipping in 2027 unable to run what is hot then — unless its architecture absorbs new compilation paths. The Infinity Engine is engineered for exactly that.
When the next model family lands — Mamba in 2023, RWKV-7 in 2025, the next thing in 2026 — the chip ships with it through a CORE compiler update, not through a silicon respin. Time-to-market on new model families collapses from quarters to days.
Architectural promise is one thing; production scope is another. The Infinity Engine is engineered to support every model family. Krsna runs four of them in real products today. We keep the two distinct — by design.
Llama · Shakti · Qwen · Gemma
Transformer-class language models. The architecture that dominates current enterprise AI workloads.
Sruthi · Svara · Moonshine · Whisper
STT and TTS pipelines. The architecture voice agents, dictation, and translation workloads depend on.
ResNet · YOLO · VGG · MobileNet
CNN inference. The architecture every camera-class device runs.
Mamba · Jamba · Mamba-2
Linear-time recurrence. SambaASR — our Mamba-based speech model — proves the chip's SSM dispatch in production.
The four production families today are what ships in real products. The architectural promise of the Infinity Engine is what makes the chip absorb what ships tomorrow — without redesigning the silicon. Four mechanisms, all engineered in.
CORE recognizes the model architecture at compile time — transformer attention vs SSM scan vs CNN convolution vs RNN recurrence — and emits the appropriate kernel sequence for the silicon. New architectures slot in as new compilation paths, not as silicon rework.
The chip's operator set is engineered to be the union of what current architectures need (matmul, attention, conv, layernorm, activation) — and the primitives future architectures will need (scan, recurrence, gating). The cost of supporting the next architecture sits on the compiler side, not the silicon side.
When a new model family emerges — RWKV, Liquid Foundation Models, the next thing — CORE absorbs it as a new compilation path for the Krsna chip. New model coverage lands in the compiler, not in a silicon redesign.
The four production families on Krsna today are what production customers run — not theoretical coverage. We say four production today; we say extensible for tomorrow. That discipline is itself a feature of the program.
"Any AI" is the chip-level architectural property delivered by the Infinity Engine — Krsna's operator-set superset and CORE's architecture-aware compilation. It is not a claim about inference throughput or token economics (that's EdgeFlow's domain). It is not a claim that every model runs at peak performance on every chip variant — Krsna Lite obviously won't run a 70B-class model.
Production scope (four families on chip today) and architectural promise (the Infinity Engine absorbs the architectures that emerge tomorrow) are kept distinct — by design. Discipline at the claim layer is the foundation that lets the chip claim work.